1. Field of the Invention
The present invention relates to nano-scale capacitors and methods for fabricating these capacitors.
2. Discussion of the Related Art
Capacitors are known in the art as devices including two conductors (with any geometry) insolated from each other so that the conductors can be given and typically hold equal, but opposite, charges. In an ideal capacitor, a positive charge (+q) that exists on one electrode is offset by a negative charge (−q) on the other electrode. The material that electrically isolates the electrodes from each other is an insulator with a specific dielectric value. The charge value at DC conditions can be determined from the following formula:Q=C×V (coulomb)where Q is total charge, C is capacitance and V is voltage. The capacitance then is a proportionality constant, relating the voltage drop between the plates to the charge on the plates.
The specific value of the capacitance is a function of the physical structure of the device. The capacitance of an ideal parallel plate capacitor is determined from the following parallel plate equation:C=∈A/d 
where ∈ is the permittivity of the dielectric material (∈=∈r∈o, where ∈r is the dielectric constant), A is the area of the plate, and d is the distance separating the plates.
FIG. 1 is a drawing of a parallel-plate capacitor. From the parallel-plate equation, the value of the capacitor can be increased by increasing the dielectric constant of the dielectric material, increasing the area of the metal plates, or decreasing the distance separating the plates.
FIG. 2 shows a parallel-plate capacitor with a positive voltage applied to the top plate and a negative voltage applied to the bottom plate. As can be seen, the electric field crosses the dielectric, offset by an induced charge in the dielectric (polarized dielectric), the amount of which depends on the dielectric constant of the dielectric material.
For comparison purposes, it is useful to calculate the area required to create a one-farad parallel-plate capacitor (PC), using the separation distance between the plates as a variable. Table 1 shows the different areas required for various separation distances. 39 million square meters is required for a 1 farad capacitor if the distance separating the plates is 1 mm. For a separation distance of 1 nm, the size required for a 1 farad capacitor would be 39 square meters, which is still a large area but 6 orders of magnitude smaller than the 1 mm separation distance. Hence, decreasing the distance can dramatically decrease the size of a parallel-plate capacitor.
TABLE 1Area of one farad parallel-plate capacitor*AreaSeparation(squareDistanceCapacitancemeters)(meters)(farads)39.0 × 1061mm1 F0.47 × 10612μm1 F39.0 × 1031μm1 F391nm1 F*Assumes dielectric constant of 2.9 PC.
Another comparison can be made by fixing the area of the capacitor and varying the distance between the plates, choosing the size used in the experiments for the PC membrane. Table 2 shows different capacitor values for a one square centimeter parallel-plate PC capacitor, again varying the separation distance between the plates. For a separation distance of 12 μm, the capacitance is 214 pF.
TABLE 2Capacitance of square centimeter parallel-plate capacitor*AreaSeparationCapacitance(cm2)Distance (meters)(farads)120μm128pF112μm214pF11μm2.57nF1100nm25.7nF11nm2.57μF*Assumes dielectric constant of 2.9 for PC.
Alternatively, the value of capacitance can increase if the area of the electrodes is increased without necessarily decreasing the separation. One advantage of capacitors is their ability to quickly provide power when needed. Capacitors are also able to repeatedly charge and discharge, without much degradation in performance. One of the issues with the utilization of capacitors in various applications has been the size of the capacitance. For example, to achieve a one farad capacitance made from parallel-plates with a separation distance of 1 mm and a dielectric constant of one would require a size of 113 million square meters, which is typically difficult if not impossible to achieve.
The following is a list of papers describing work on the generation of advanced capacitors. The entire contents of each of the following are incorporated herein by reference.                1. Cortie, M. B. et al., 2005. “Conduction, Storager, and Leakage . . . ,” IEEE Trans. On Nanotechnology, Vol. 4, No. 4, July 2005, pp. 406-414.        2. Ionescu-Zanetti, C. et al., 2006. “Nanogap capacitors . . . ,” J. of Appl. Phys., 99, 024305, (pp. 024305-1-024305-5).        3. Stengel. S. and N. A. Spaldin. 2006. “Origin of the dielectric . . . ,” Nature, Vol. 443, pp. 679-682.        4. Sohn, J. I. et al. 2005. “Fabrication of high-density . . . ,” Appl. Phys. Letters 87, 123115 (pp. 123115-1-123115-3),        5. Klootwijk, J et al. 2006. “Extremely High-Density Capacitors with ALD High-k Dielecric Layers,”. pp. 17-28, in Defects in High-k Gate Dielectric Stacks, Edited by E. Gusev, Published by Springer Verlag.        6. Kemell, M. et al. 2007. “Si/Al2O3/ZnO:Al capacitor arrays in electrochemically etched Si . . . ”, Microelectronic Engineering 84, pp. 313-318.        7. Black, C. T., et al. 2004, “High-capacity, Self-Assembled MOS Decoupling Capacitors,” IEEE Electron Device Letters, vol. 25, No. 9, pp. 622-624.        
Capacitors described in the above papers (1-4) were built using technologies which are different than those described here. Moreover, the capacitors described in the papers (5-7) were built in silicon, and have applications in microelectronics, primarily as bypass capacitors.
Further work relevant to the various techniques described herein are described in the following papers, the entire contents of each of the following are incorporated herein by reference.                8. Lee, J., K. Batley, and O. A. Palusinski, 2005. “Electrodeposition in Nanostructure Templates Using Novel Cathode Preparation,” Electrochemical Transaction, Vol. 1(12), 25.        9. Enculescu, I., Z. Siwy, D. Dobrev, C. Trautmann, E. M. Toimil-Molares, R. Neumann, K. Hjort, L. Westerberg, R. Spohr, 2003. “Copper nanowires electrodeposited in etched single-ion track templates,” App. Phys. A: Mater. Sci. Process. 77, 751-755.        10. Siwy, Z., A. Fuliński. 2002. “Fabrication of a Synthetic Nanopore Ion Pump,” Phys. Rev. Lett. 89, 198103 (1-4).        11. Siwy, Z., 2006. “Ion Current Rectification in Nanopores and Nanotubes with Broken Symmetry—Revisited,” Advanced Functional Materials, 16, 735-746.        12. J. Lee, K. Batley, and O. A. Palusinski, 2006. “Electrical Characterization of Nano Structured Energy Storage Device,” Electrochemical Transaction, Vol. 2, in printing.        13. Guzman, R., J. Lee, O. A. Palusinski, Z. Siwy, 2004. “Universal Bonding Structure for Electronic Chips and Packages—Nano-scale interconnects,” Invention Disclosure, Univ. of Arizona, Office of Technology Transfer.         14. Lee, J., K. L. Bartley, and O. A. Palusinski, 2004a. “Gold Nano-structures Built in Polycarbonate Templates,” Interim Report, Dept. of ECE, University of Arizona.         15. Lee, J., K. L. Bartley, and O. A. Palusinski, 2004b. “Fabrication of Gold Nano-Wires via Electrodeposition in Templates,” Interim Report, Dept. of ECE, University of Arizona.         16. Lee, J., Z. Siwy, K. L. Bartley, T. Zhu, D. Zhang, and O. A. Palusinski, 2004. “Nano Wire Fabrication Using Templates,” Interim Report, Dept. of ECE, University of Arizona.         17. Masuda, H., H. Yamada, M. Satoh, H. Asoh, M. Nakao, and T. Tamamura, 1997. “Highly ordered nanochannel-array architecture in anodic alumina,” Appl. Phys. Lett. 71 (19), 2770-2772.        18. Jessensky, O., F. Müller, and U. Gösele, 1998. “Self-organized formation of hexagonal pore arrays in anodic alumina,” Appl. Phys. Lett. 72 (10), 1173-1175.        19. Vetter, J. and R. Spohr, 1993. “Application of ion track membranes for preparation of metallic microstructures,” Nucl. Instrum. Methods Phys. Res., Sect. B, 79, 691-694.        